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Joonyoung Seo

Integrated M.S.–Ph.D. Program, CSDL, POSTECH (Korea)

Education

BSc in Department of Electrical Engineering

POSTECH
2019 - 2023

Integrated M.S.–Ph.D. Program in Department of Electrical Engineering

POSTECH
2023 - Present

Languages

  • Korean (Native)
  • English (Normal)

Career Profile

I received the B.S. degree in Electrical Engineering in 2023 from POSTECH. I am currently in the integrated M.S.–Ph.D. program at CSDL, POSTECH.

Experiences

Intern

2022
SK Hynix

Researched and developed verification of SRAM with UVM(Universal Verification Methodology).

Projects

3rd Prize in AIX Deep Learning Hardware Design Contest - July 2022

Publications

  • Thermal-Aware Floorplanning for 3D ICS
    • Joonyoung Seo, Seokhyeong Kang
    Korean Conference on Semiconductors 2023
  • Enhancing Timing Closure via Spatially Embedded Graph Transformer with Low Power/Area Overhead
    • Joonyoung Seo, Jonghyeon Nam, Howoo Jang, Yoonseok Jung, Seokhyeong Kang
    Internation Conference on Computer-Aided Design 2025

    Skills & Proficiency

    Python

    C++

    Matlab

    Verilog